With recent advancements in integrated circuit (IC) processing and/or designing techniques, the role of adders to complement the continuously advancing data processing technology have also increased. Adders are considered pivotal for the operations of computers, processors, and/or other digital integrated circuits, such as Digital Phase Locked Loops (DPLL) circuits, Multiply-Accumulate (MAC) circuits for Digital Signal Processors (DSP) and/or circuits that require transmission of high speed data for the generation of high frequency clock sources.
Currently, most of the digital ICs perform data processing operations on a single pair of numbers at a time. The data processing operations are usually tailored to handle large numbers that require numerous bits for representation. In certain scenarios, when the data processing operations are required to handle large quantity of small numbers, the conventional data processing techniques by use of conventional adders incur penalties to processing performance related to latency, power, and/or area. Hence, an efficient technique or mechanism may be required to process data in an advanced adder based circuit, where multiple addends may be added and/or subtracted in an optimized manner.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of described systems with some aspects of the present disclosure, as set forth in the remainder of the present application and with reference to the drawings.